In processing mixed analog and digital signals, one of the most important factors for good performance of an analog circuit, as part of a mixed signal circuit, is the amount of jitter in bandwidth of interest of the analog circuit. Jitter manifests itself as unwanted variation in the interval between clock pulses. This factor is extremely important in situations where the analog part of the circuitry uses a digital clock for its sampling or over-sampling clock (e.g. analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).
In the digital era, where the trend is to use as many digital circuits as possible, digital clock synthesizers (i.e. DCOs) are used more and more to create sampling clocks for different analog circuits. DCO generated clocks have uniformly distributed jitter ranging from DC up to half of the clock carrier frequency. Since this bandwidth always includes the range of interest of most mixed signal circuits, there is a need for a circuit that can shift digital jitter into high frequency area, outside the range of interest, where the performance of the circuits is not affected.
In previous implementations, e.g. ADC and DAC converters, a clean clock from a crystal oscillator was used as a sampling clock. When a network clock, or clock from a digital source, such as DCO, had to be used as sampling clock, the DCO output clock was first filtered with an analog phase locked loop (APLL) before being used.
U.S. Pat. No. 6,396,313 describes a jitter shaping circuit. This jitter shaper has a low efficiency since changes in jitter due to jitter shaping are not considered when making decisions about further jitter shaping.